Low voltage rail-to-rail CMOS input stage

ABSTRACT

The present invention discloses a low voltage rail-to-rail CMOS input stage. The input stage includes a differential pail of P-channel metal oxide semiconductor field effect (PMOS) transistors, which produces differential output current signal. The input stage further includes a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors, coupled to the bulk terminals of the differential pair of PMOS transistors, for receiving an input signal. The depletion-mode NMOS transistors further act as source follower devices to drive the bulk terminals of the differential pair of PMOS transistors.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. patent application Ser. No.9/516,008 entitled LOW VOLTAGE RAIL-TO-RAIL CMOS INPUT STAGE, filed onFeb. 29, 2000 now U.S. Pat. No. 6,366,167. This application is relatedto co-pending U.S. patent application Ser. No. 9/515,961 entitled LOWVOLTAGE RAIL-TO-RAIL CMOS OUTPUT STAGE, filed on an even day herewith onbehalf of Troy L. Stockstad, the disclosure of which is incorporatedherein by reference.

BACKGROUND OF THE INVENTION

The present invention relates generally to integrated circuits and, moreparticularly to amplifiers having a low voltage CMOS differentialamplifier input stage.

Today, electronic systems encompassing operational amplifiers generallyhave lower operating voltage supplies than they have in the past, mainlydo to low power battery sources. Moreover, power supply voltagesrequirements continue to decrease, while dynamic range requirementsremain essentially constant. Fortunately, various manufacturingprocesses for integrated circuits make it possible to createrail-to-rail differential input stages.

Although the various types of input stages operate from a single supplyvoltage source, the low voltage limit for amplifier operation differsfor each type of input stage and each integrated circuit manufacturingprocess. Present op amp input stage designs exhibit voltage operationlimits that hinder their application in products powered by batterieshaving an end life of near one volt. For example, an op amp usingcomplimentary bipolar transistor differential pairs amplifying signalsnear positive and negative supplies has low operating voltagelimitations imposed by standard transistor base to emitter voltagedrops.

One conventional solution for rail-to-rail input stages has been the useof depletion-mode MOSFETs to provide amplification of the differentialinput. FIG. 1 is a schematic diagram showing a prior art input stage 100for a low voltage operational amplifier. The input stage 100 includes adifferential input signal V_(IN) coupled to the gates of two N-channeldepletion-mode MOSFETs 2 and 4. The drain of MOSFET 2 is coupled to oneterminal of current source 6, and the drain of MOSFET 4 is coupled toone terminal of current source 8. The second terminals for both currentsources 6 and 8 are coupled to operating potential V_(CC). Both sourceterminals of MOSFETs 2 and 4 are coupled to one terminal of current sink10, while the other terminal of current sink 10 is coupled to groundreference. The bulk, or well, terminals of both MOSFET 2 and MOSFET 4are also coupled to the ground reference.

The differential pair of MOSFETs 2 and 4 receives the input signalV_(IN) and provides a differential output current from the drainterminals of MOSFETs 2 and 4 at inputs 14 and 16 to the rest of thesystem. While the prior art input stage 100 provides an inputtransconductance, input stage 100 has limited uses. For example, inputstage 100 requires the input NMOS transistors 2 and 4 to have aparticular combination of threshold voltage and bulk concentration tohave proper common mode range and function correctly. This causes theprocess requirements for input stage 100 to be strictly defined so thatthe common mode input range is maximized.

In view of the forgoing, what is needed is a versatile operationalamplifier input stage that can be used in a variety of applicationspowered from battery sources. In addition, the amplifier input stageshould allow near rail-to-rail performance and increased designflexibility over that provided by prior art input stages.

SUMMARY OF THE INVENTION

The present invention addresses these needs by providing a low voltagerail-to-rail CMOS input stage. In one embodiment, a low voltageoperational amplifier input stage is disclosed. The input stage includesa differential pair of P-channel metal oxide semiconductor field effect(PMOS) transistors, which produces a differential current. The inputstage further includes two N-channel depletion-mode metal oxidesemiconductor field effect (NMOS) transistors, coupled to the bulkterminals of the differential pair of PMOS transistors, for receiving aninput signal. The depletion-mode NMOS transistors further act as sourcefollower devices to drive the bulk terminals of the differential pair ofPMOS transistors.

In another embodiment, a method for providing an output signal from aninput stage of a low voltage operational amplifier is disclosed. Themethod includes providing an input signal to two NMOS transistorscoupled to bulk terminals of a differential pair of PMOS transistors.The method further includes providing first and second alternatingcurrent signals using the differential pair of PMOS transistors.

An application specific integrated circuit (ASIC) having an input stagefor a low voltage operational amplifier input stage is disclosed. TheASIC includes a differential pair of P-channel metal oxide semiconductorfield effect (PMOS) transistors, which produces a differential outputcurrent. The ASIC further includes two N-channel depletion-mode metaloxide semiconductor field effect (NMOS) transistors, coupled to the bulkterminals of the pair of PMOS transistors, for receiving an inputsignal. The depletion-mode NMOS transistors further act as sourcefollower devices to drive the bulk terminals of the differential pair ofPMOS transistors.

In yet another embodiment, a low voltage operational amplifier inputstage is disclosed. The input stage includes a differential pair of NMOStransistors, which produces a differential current. The input stagefurther includes two depletion-mode PMOS transistors coupled to the bulkterminals of the differential pair of NMOS transistors, for receiving aninput signal. The depletion-mode PMOS transistors further act as sourcefollower devices to drive the bulk terminals of the differential pair ofNMOS transistors.

In a still further embodiment, a low voltage operational amplifier inputstage is disclosed. The input stage includes a differential pair of NMOStransistors, which produces a differential current. The input stagefurther includes two JFET transistors coupled to the bulk terminals ofthe differential pair of NMOS transistors, for receiving an inputsignal. The JFET transistors further act as source follower devices todrive the bulk terminals of the differential pair of NMOS transistors.

Advantageously, the present invention provides a versatile operationalamplifier input stage that can be used in a variety of applications,including applications powered by low power battery sources. Moreover,the input stage of the present invention provides essentiallyrail-to-rail performance and increased design flexibility over thatprovided by conventional input stages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a prior art input stage for a lowvoltage operational amplifier;

FIG. 2 is a block diagram showing an operational amplifier, inaccordance with one embodiment of the present invention;

FIG. 3 is a block diagram showing an input stage, in accordance with anembodiment of the present invention;

FIG. 4 is a schematic diagram showing an input stage in accordance withanother embodiment of the present invention;

FIG. 5 is graph showing a plot of the source voltage vs. the gatevoltage of a depletion-mode NMOS transistor, in accordance with anembodiment of the present invention;

FIG. 6A is a schematic diagram of a low voltage rail-to-rail CMOS inputstage, in accordance with one embodiment of the present invention;

FIG. 6B is a schematic diagram of a low voltage rail-to-rail CMOS inputstage, in accordance with another embodiment of the present invention;and

FIG. 7 is a schematic diagram showing a one volt rail-to-rail CMOS inputstage, in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

An invention is disclosed for a low voltage rail-to-rail CMOS inputstage. In the following description, numerous specific details are setforth in order to provide a thorough understanding of the presentinvention. It will be apparent, however, to one skilled in the art, thatthe present invention may be practiced without some or all of thesespecific details. In other instances, well known process steps anddevices have not been described in detail in order not to unnecessarilyobscure the present invention.

FIG. 1 has been described in terms of the prior art. FIG. 2 is a blockdiagram showing an operational amplifier 150, in accordance with oneembodiment of the present invention. The operational amplifier 150includes an input stage 200 and an output stage 201.

In operation, the input stage 200 receives a differential input signalV_(IN). The input stage 200 then converts the differential input signalto an output signal and supplies the output signal to the output stage201. The output stage 201 receives the input stage output signal andconverts it to an amplified output voltage V_(O).

The output stage 201 provides essential rail-to-rail performance, and iscapable of operating with a voltage supply as low as slightly more thana single V_(GS) voltage. As described in greater detail subsequently,the use of an output sink and source network by the output stage 201allows this functionality.

FIG. 3 is a block diagram showing an input stage 200, in accordance withan embodiment of the present invention. The input stage 200 includes avoltage input network 202 and transconductance network 204 coupled tothe voltage input network 202. The voltage input network 202 receives adifferential input signal V_(IN), while the transconductance network 204provides differential current I₀ to the rest of the system, such as toan operational amplifier.

It is desirable to generate a current based on the differential inputvoltage over the entire common-mode range of the amplifier, includingV_(CC) and V_(EE). Thus, in operation, input stage 200 provides currentfor rail-to-rail operation at low voltage, as is often required by lowpower battery sources. Conventional transconductance networks generallyhave a limited input common mode voltage range over which they cangenerate current, which does not include V_(CC) and V_(EE). However, thepresent invention allows essentially full rail-to-rail performancebecause the voltage input network 202 allows the transconductancenetwork 204 to generate current over a voltage range of essentially fromV_(EE) to V_(CC).

FIG. 4 is a schematic diagram showing an input stage 300 in accordancewith another embodiment of the present invention. The input stage 300includes a voltage input network 202 and a transconductance network 204.The voltage input network 202 includes depletion-mode NMOS transistor302 and depletion-mode NMOS transistor 304. The drains of depletion-modeNMOS transistors 302 and 304 are coupled to V_(CC) and the sources ofdepletion-mode NMOS transistors 302 and 304 are coupled to thetransconductance network 204. Finally, the differential input signalV_(IN) is provided to the voltage input network 202 through the gates ofdepletion-mode NMOS transistors 302 and 304.

In use, the depletion-mode NMOS transistors 302 and 304 are used assource follower devices to drive the transconductance current network204. Advantageously, the depletion-mode NMOS transistors 302 and 304have a source potential greater than V_(EE) when their gate voltages areequal to V_(EE). Moreover, when the gate voltage of the depletion-modeNMOS transistors 302 and 304 transitions to near V_(CC), the back-gateeffect on these transistors causes the threshold to become positive,thus making the source voltage less than the gate voltage. As describedin greater detail subsequently, this property of the depletion-mode NMOStransistors 302 and 304 allows the input stage of the present inventionto operate over a common mode voltage range, which includes V_(CC) andV_(EE).

FIG. 5 is graph 400 showing a plot of the source voltage vs. the gatevoltage of a depletion-mode NMOS transistor, in accordance with anembodiment of the present invention. The graph 400 includes avoltage-gate axis 402, a voltage-source axis 404, and a plot of thesource voltage 406 in relation to the gate voltage. As shown by graph400, when the gate voltage is at V_(EE), the source voltage is positive,at about 200 mV, and when the gate voltage is at 1V, the source voltageis about 900 mV. Thus, the source range for the depletion-mode NMOStransistors of the present invention is about 200 mV to 900 mV, whichallows these devices to drive the bulk terminals of PMOS transistors, asdescribed in greater detail subsequently. Essentially, the depletionmode NMOS transistors compress the full scale input voltage to a rangewithin the supply voltages V_(CC) and V_(EE).

Depletion-mode NMOS transistors are generally built on a siliconsubstrate having four terminals represented as gate, drain, source, andbulk. A processing mask layer defines the region for implanting N-typedoping material, such as arsenic, into the silicon to form source anddrain regions. The MOS gate region is also defined by a processing masklayer such that the gate conductor and gate oxide physically separatethe source and drain regions. N-channel source and drain regions areconfined within a well region for receiving a p-type material implant,such as boron. The background concentration of the well regiondetermines the back gate effect, which controls the change in thethreshold voltage determined by the source to bulk voltage. Lowresistance conducting materials, such as aluminum metal, provideelectrical connections to the gate terminal, source terminal, drainterminal, and the bulk terminal.

FIG. 6A is a schematic diagram of a low voltage rail-to-rail CMOS inputstage 500, in accordance with one embodiment of the present invention.The input stage 500 includes a voltage input network 202 and atransconductance network 204. The voltage input network 202 includesdepletion-mode NMOS transistor 302 and depletion-mode NMOS transistor304. The drains of depletion-mode NMOS transistors 302 and 304 arecoupled to V_(CC) and the sources of depletion-mode NMOS transistors 302and 304 are coupled to the transconductance network 204. Finally, thedifferential input signal V_(IN) is provided to the voltage inputnetwork 202 through the gates of depletion-mode NMOS transistors 302 and304.

In use, the depletion-mode NMOS transistors 302 and 304 are used assource follower devices to drive the transconductance network 204.Advantageously, the depletion-mode NMOS transistors 302 and 304 have asource potential greater than V_(EE) when their gate voltages are equalto V_(EE). Moreover, when the gate voltage the depletion-mode NMOStransistors 302 and 304 transitions to near V_(CC), the back-gate effecton these transistors causes their threshold voltages to become positive,thus making their source voltages less than their gate voltages. Thisproperty of the depletion-mode NMOS transistors 302 and 304 allows theinput stage of the present invention to operate at essentiallyrail-to-rail.

The transconductance network 204 includes a differential PMOS transistorpair 502 and 504. The gates of PMOS transistors 502 and 504 are coupledto the ground reference V_(EE), and the sources of PMOS transistors 502and 504, are coupled to current source 506. The drains of PMOStransistors 502 and 504 provide a differential output I₀ to the rest ofthe system, such as to an operational amplifier. Finally, the bulkterminal of PMOS transistor 502 is coupled to the source ofdepletion-mode NMOS transistor 302, and the bulk terminal of PMOStransistor 504 is coupled to the source of depletion-mode NMOStransistor 304.

Essentially, it is desirable to generate a current based on adifferential input voltage over the entire common-mode range of theamplifier, including V_(CC) and V_(EE). The present invention addressesthis by driving the bulk terminals of the differential pair PMOStransistors 502 and 504, and coupling their gates to the groundreference. Thus, in operation, the depletion-mode NMOS transistors 302and 304 are utilized as source follower devices to drive the bulkterminals of PMOS transistors 502 and 504. By modulating the bulkvoltages of PMOS transistors 502 and 504 via the source follower NMOStransistors 302 and 304, the channels of transistors 502 and 504 aresufficiently modulated to generate an input transconductance for theamplifier.

The bulk terminals of transistors 502 and 504 can be treated as anothergate input to the PMOS transistor, thus, allowing the present inventionto operate over the entire input common-mode range of V_(CC) to V_(EE).In the present invention, the range of voltages over which a current canbe generated matches the input ranges of the depletion-mode transistors.

Since the bulk terminals of NMOS transistors 302 and 304 are coupled toV_(EE), when the gate voltage of these transistors is at V_(EE) thesource voltage will be positive (i.e., above the gate). Moreover, whenthe gate voltage transistors 302 and 304 transitions to near V_(CC), theback-gate effect on these transistors causes their threshold voltages tobecome positive, thus making their source voltages less than their gatevoltages, as discussed previously with reference to FIG. 5.

These depletion-mode devices are primarily used for a voltage levelshifter in the present invention, rather than to control thetransconductance. This allows for greater flexibility than is possiblewith prior art configurations. For example, the devices may havedifferent sizes and thus have a different transconductance withouteffecting the bandwidth of the operational amplifier. This is becausethe current in the differential pair transistors 502 and 504, and thesize of these devices, set the bandwidth of the operational amplifier,along with the compensation network in output stage 201.

FIG. 6B is a schematic diagram of a low voltage rail-to-rail CMOS inputstage 600, in accordance with another embodiment of the presentinvention. The embodiment in FIG. 6B is the dual of the embodiment of inFIG. 6A. The input stage 600 includes a voltage input network 602 and atransconductance network 604. The voltage input network 602 in FIG. 6Bincludes PMOS transistors 308 and 310. Also, the transconductancenetwork 604 includes a differential NMOS transistor pair 510 and 512. Ascan be appreciated by those with skill in the art, the embodiment ofFIG. 6B performs similar to the embodiment of FIG. 6A. In yet anotherembodiment, the PMOS transistors in FIG. 6B can be replaced with JFETtransistors.

The choice between the embodiment in FIG. 6A and the embodiment in FIG.6B essentially depends on the process being implemented. Depending onthe process, one of the embodiments may be easier to implement. However,both will provide the essentially same function.

FIG. 7 is a schematic diagram showing a one volt rail-to-rail CMOS inputstage 700, in accordance with another embodiment of the presentinvention. The input stage 700 includes depletion-mode NMOS transistor302, depletion-mode NMOS transistor 304, and a transconductance network204. The drains of depletion-mode NMOS transistors 302 and 304 arecoupled to V_(CC) and the sources of depletion-mode NMOS transistors 302and 304 are coupled to the transconductance network 204. Finally, thedifferential input signal V_(IN) is provided through the gates ofdepletion-mode NMOS transistors 302 and 304.

In use, the depletion-mode NMOS transistors 302 and 304 are used assource follower devices to drive the transconductance network 204.Advantageously, the depletion-mode NMOS transistors 302 and 304 have asource potential greater than V_(EE) when their gate voltages are equalto V_(EE). Moreover, when the gate voltages of the depletion-mode NMOStransistors 302 and 304 transitions to near V_(CC), the back-gate effecton these transistors causes their threshold voltages to become positive,thus making their source voltages less than their gate voltages. Thisproperty of the depletion-mode NMOS transistors 302 and 304 allows theinput stage of the present invention to operate at essentiallyrail-to-rail.

The transconductance network 204 includes a differential PMOS transistorpair 502 and 504. The gates of PMOS transistors 502 and 504 are coupledto the ground reference V_(EE), and the sources of PMOS transistors 502and 504, are coupled to current source 506. The drains of PMOStransistors 502 and 504 provide differential output current I₀ to therest of the system, such as to an operational amplifier. Finally, thebulk terminal of PMOS transistor 502 is coupled to the source ofdepletion-mode NMOS transistor 302, and the bulk terminal of PMOStransistor 504 is coupled to the source of depletion-mode NMOStransistor 304.

Essentially, it is desirable to generate a current based on adifferential input voltage over the entire common-mode range of theamplifier, including V_(CC) and V_(EE). The present invention addressesthis by driving the bulk terminals of the differential pair PMOStransistors 502 and 504, and coupling their gates to the groundreference. Thus, in operation, the depletion-mode NMOS transistors 302and 304 are utilized as source follower devices to drive the bulkterminals of PMOS transistors 502 and 504. By modulating the bulkvoltages of PMOS transistors 502 and 504 via the source follower NMOStransistors 302 and 304, the channels of transistors 502 and 504 aresufficiently modulated to generate an input transconductance for theamplifier.

The bulk terminals of transistors 502 and 504 can be treated as anothergate input to the PMOS transistor, thus, allowing the present inventionto operate over the entire input common-mode range of V_(CC) to V_(EE).In the present invention, the range of voltages over which a current canbe generated matches the input ranges of the depletion-mode transistors.

Since the bulk terminals of NMOS transistors 302 and 304 are coupled toV_(EE), when the gate voltage of these transistors is at V_(EE) thesource voltage will be positive (i.e., above the gate). Moreover, whenthe gate voltage transistors 302 and 304 transitions to near V_(CC), theback-gate effect on these transistors causes their threshold voltages tobecome positive, thus making their source voltages less than their gatevoltages, as discussed previously with reference to FIG. 5.

The input stage 700 further includes NMOS transistors 702 and 704, whichoperate as current sources, a current mirror 705 having PMOS transistors706 and 708, and a folded cascode 709 having NMOS transistors 710 and712. In operation, the current mirror 705 is used to create adifferential-to-single-ended conversion to the output V_(O), wheretransistors 714 and 716 act as current sources. The current from thetransconductance network 204 subtracts from the drain currents oftransistors 714 and 716. The differential current is then applied to thefolded cascode 709, where the current from transistor 712 is replicatedby the current mirror 705, and compared to the current in transistor 710at the output V_(O).

While the present invention has been described in terms of severalpreferred embodiments, there are many alterations, permutations, andequivalents which may fall within the scope of this invention. It shouldalso be noted that there are many alternative ways of implementing thesystems and apparatuses of the present invention. It is thereforeintended that the following appended claims be interpreted as includingall such alterations, permutations, and equivalents as fall within thetrue spirit and scope of the present invention.

1. A low voltage operational amplifier input stage, the input stagecomprising: a differential pair of P-channel metal oxide semiconductorfield effect (PMOS) transistors, wherein the PMOS transistors produce afirst and second current signal; a pair of N-channel depletion-modemetal oxide semiconductor field effect (NMOS) transistors coupled withthe differential pair of PMOS transistors for receiving an input signaland for acting as source follower devices; and wherein each PMOStransistor has a bulk terminal, and wherein the pair of N-channeldepletion mode metal oxide semiconductor field effect (NMOS) transistorsis coupled to the bulk terminals of the differential pair of PMOStransistors, and act as source follower devices to drive the bulkterminals of the differential pair of PMOS transistors.
 2. An inputstage as recited in claim 1, wherein the input signal is a differentialinput signal that is coupled to gate terminals of the depletion-modeNMOS transistors.
 3. An input stage as recited in claim 1, wherein gateterminals of the differential pair of PMOS transistors are coupled toground, and wherein source terminals of the differential pair of PMOStransistors are coupled to a current source.
 4. An input stage asrecited in claim 1, wherein the bulk terminals of the depletion-modeNMOS transistors are coupled to ground reference, and the drainterminals of the depletion-mode NMOS transistors are coupled to V_(CC).5. An input stage as recited in claim 4, wherein the source terminals ofthe depletion-mode NMOS transistors are coupled to the bulk terminals ofthe differential pair of PMOS transistors.
 6. An input stage as recitedin claim 1, wherein the source terminal of each of the depletion-modeNMOS transistors has a voltage greater than V_(EE) when the gate voltageof each of the depletion-mode NMOS transistors has a voltage equal toV_(EE).
 7. An input stage as recited in claim 5, wherein the sourceterminals of each of the depletion-mode NMOS transistors has a voltageless than V_(CC) when the gate voltage of each of the depletion-modeNMOS transistors has a voltage equal to V_(CC).
 8. A method forproviding an output signal from in input stage of a low voltageoperational amplifier, the method comprising the operations of:providing an input signal to a pair of N-channel depletion-mode metaloxide semiconductor field effect (NMOS) transistors coupled to bulkterminals of a differential pair of P-channel metal oxide semiconductorfield effect (PMOS) transistors, such that said NMOS transistors act asa source follower.
 9. A method as recited in claim 8, wherein theoperation of providing an input signal to the depletion-mode NMOStransistors includes applying a differential input signal to gateterminals of the depletion-mode NMOS transistors.
 10. A method asrecited in claim 9, wherein gate terminals of the differential pair ofPMOS transistors are coupled to ground, and wherein source terminals thedifferential pair of PMOS transistors are coupled to a current source.11. A method as recited in claim 8, wherein the bulk terminals of thedepletion-mode NMOS transistors are coupled to V_(EE), and the drainterminals of the depletion NMOS transistors are coupled to V_(CC).
 12. Amethod as recited in claim 11, wherein the source terminals of thedepletion-mode NMOS transistors are coupled to the bulk terminals of thedifferential pair of PMOS transistors.
 13. A method as recited in claim8, wherein the source terminal of each of the depletion-mode NMOStransistors has a voltage greater than V_(EE) when the gate voltage ofeach of the depletion-mode NMOS transistors has a voltage equal toV_(EE).
 14. A method as recited in claim 8, wherein the source terminalof each of the depletion-mode NMOS transistors has a voltage less thanV_(CC) when the gate voltage of each of the depletion mode NMOStransistors has a voltage equal to V_(CC).
 15. An application specificintegrated circuit (ASIC) comprising: a differential pair of P-channelmetal oxide semiconductor field effect (PMOS) transistors, each PMOStransistor having a bulk terminal, wherein the PMOS transistors areoperative to produce a differential current signal; and a pair ofN-channel depletion-mode metal oxide semiconductor field effect (NMOS)transistors, coupled to the bulk terminals of the differential pair ofPMOS transistors, for receiving an input signal and for acting as sourcefollower devices to drive the differential pair of PMOS transistors. 16.An ASIC as recited in claim 15, wherein the input signal is adifferential input signal that is coupled to gate terminals of thedepletion-mode NMOS transistors.
 17. An ASIC as recited in claim 15,wherein gate terminals of the differential pair of PMOS transistors arecoupled to V_(EE), and wherein source terminals the differential pair ofPMOS transistors are coupled to a current source.
 18. An ASIC as recitedin claim 15, wherein the source terminal of each of the depletion-modeNMOS transistors has a voltage greater than V_(EE) when the gate voltageof each of the depletion-mode NMOS transistors has a voltage equal toV_(EE).
 19. An ASIC as recited in claim 18, wherein the source terminalof each of the differential pair of depletion-mode NMOS transistors hasa voltage less than V_(CC) when the gate voltage of each of thedifferential pair of depletion-mode NMOS transistors has a voltage equalto V_(CC).
 20. An operational amplifier input stage, the input stagecomprising: a voltage input network, wherein the voltage input networkreceives a differential input signal, and wherein the voltage inputnetwork provides a voltage input network output signal; atransconductance network, wherein the transconductance network receivesthe voltage input network output signal, and wherein thetransconductance network provides a differential output signal; whereinthe voltage input network is operative to act as a source followerdevice and drive the transconductance network; and wherein the voltageinput network includes a pair of depletion-mode NMOS transistors.
 21. Anoperational amplifier input stage, the input stage comprising: a voltageinput network, wherein the voltage input network receives a differentialinput signal, and wherein the voltage input network provides a voltageinput network output signal, the voltage input output signal being abovethe V_(EE) when the differential input signal is at V_(EE) and whereinthe voltage input network includes a pair of depletion-mode NMOStransistors; an transconductance network, wherein the transconductancenetwork receives the voltage input network output signal, and whereinthe transconductance network provides a differential output signal andwherein the transconductance network includes a differential pair ofPMOS transistors, each PMOS transistor having a bulk terminal; andwherein the voltage input network is operative to act as a sourcefollower device and drive the transconductance network.
 22. Anoperational amplifier input stage as recited in claim 21, wherein thedepletion-mode NMOS transistors drive the bulk terminals of thedifferential pair of PMOS transistors.
 23. An operational amplifierinput stage as recited in claim 20, wherein a source terminal of each ofthe depletion-mode NMOS transistors has a voltage greater than V_(EE)when a gate voltage of each of the depletion-mode NMOS transistors has avoltage equal to V_(EE).
 24. An operational amplifier input stage asrecited in claim 23, wherein the source terminal of each of thedepletion-mode NMOS transistors has a voltage less than V_(CC) when thegate voltage of each of the depletion-mode NMOS transistors has avoltage equal to V_(CC).
 25. An operational amplifier capable ofoperating on low supply voltages, the operational amplifier comprising:an input stage having a differential pair of PMOS transistors, and anoutput stage, wherein each the PMOS transistor includes a bulk terminal,and wherein the differential pair of PMOS transistors produces adifferential output signal, and wherein the NMOS transistors aredepletion-mode NMOS transistors, and wherein the of depletion-mode NMOStransistors are coupled to the bulk terminals of the differential pairof PMOS transistors.
 26. An operational amplifier as recited in claim25, wherein the depletion-mode NMOS transistors receive a differentialinput signal using the gate terminals of the NMOS transistors.
 27. Anoperational amplifier as recited in claim 25, wherein the PMOStransistors are coupled to a folded cascode circuit.
 28. An operationalamplifier as recited in claim 27, wherein the folded cascode circuitincludes a pair of NMOS transistors.
 29. A low voltage operationalamplifier input stage, the input stage comprising: a plurality ofN-channel metal oxide semiconductor field effect (NMOS) transistors,each NMOS transistor having a bulk terminal, for producing a first and asecond current signal; and a plurality of P-channel depletion-mode metaloxide semiconductor field effect (PMOS) transistors, coupled to eachbulk terminal of the plurality of NMOS transistors, for acting as sourcefollower devices to drive the plurality of NMOS transistors.
 30. Aninput stage as recited in claim 29, wherein the input signal is adifferential input signal that is coupled to gate terminals of thedepletion-mode PMOS transistors.
 31. A low voltage operational amplifierinput stage, the input stage comprising: a plurality of N-channel metaloxide semiconductor field effect (NMOS) transistors for producing afirst and a second current signal wherein gate terminals of the NMOStransistors are coupled to V_(CC); and a plurality of P-channeldepletion-mode metal oxide semiconductor field effect (PMOS) transistorsfor acting as source follower devices to drive the plurality of NMOStransistors, and wherein source terminals of the PMOS transistors arecoupled to a current source.
 32. A low voltage operational amplifierinput stage, the input stage comprising: a plurality of N-channel metaloxide semiconductor field effect (NMOS) transistors for producing afirst and a second current signal; and a plurality of P-channeldepletion-mode metal oxide semiconductor field effect (PMOS) transistorsfor acting as source follower devices to drive the plurality of NMOStransistors signal wherein the drain terminals of the depletion-modePMOS transistors are coupled to V_(EE).
 33. An input stage as recited inclaim 32, wherein the source terminals of the depletion-mode PMOStransistors are coupled to bulk terminals of the NMOS transistors.
 34. Alow voltage operational amplifier input stage, the input stagecomprising: a differential pair of first transistors, each transistorhaving a bulk terminal, operative to produce a first and a secondcurrent signal; and a pair of second transistors, coupled to the bulkterminals of the differential pair of first transistors, for receivingan input signal and for acting as source follower devices to drive thedifferential pair of first transistors.
 35. The apparatus of claim 34,wherein said first transistors are chosen from the group consistingessentially of JFET transistors, NMOS transistors and PMOS transistors,and wherein said second transistors are chosen from the group consistingessentially of JFET transistors, NMOS transistors and PMOS transistors.36. An operational amplifier input stage, the input stage comprising: atransconductance network, having a plurality of bulk terminals, forproviding a current output signal in response to a voltage outputsignal; and a voltage input network, coupled to the plurality of bulkterminals, for providing the voltage output signal, wherein the voltageinput network is operative to act as a source follower device and drivethe transconductance network.
 37. The operational amplifier input stageof claim 36, wherein the transconductance cicuit is coupled to a foldedcascode circuit.